CPU Architecture Basics
CPU Architecture Basics¶
Overview¶
The CPU (Central Processing Unit) is the brain of the computer, serving as the core component that interprets and executes program instructions. In this lesson, we'll learn in detail about the internal components of the CPU, types of registers, datapath structure, and the instruction execution cycle.
Difficulty: ββ
Prerequisites: Logic Gates, Sequential Logic Circuits, Combinational Logic Circuits
Table of Contents¶
- CPU Components
- Register Types
- Datapath
- Instruction Execution Cycle Details
- Single-Cycle vs Multi-Cycle
- Practice Problems
1. CPU Components¶
1.1 Overall CPU Structure¶
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β CPU β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β Control Unit β β
β β βββββββββββββββ βββββββββββββββ βββββββββββββββββββββββ β β
β β β Instruction β β Control β β Timing & Sequencingβ β β
β β β Decoder β β Signal β β (Sequencer) β β β
β β β β β Generator β β β β β
β β βββββββββββββββ βββββββββββββββ βββββββββββββββββββββββ β β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β
β βββββββββββββββββββββββ βββββββββββββββββββββββββββββββββββ β
β β Register File β β ALU (Arithmetic Logic β β
β β βββββββ βββββββ β β Unit) β β
β β β R0 β β R1 β β β βββββββββββββββββββββββββββ β β
β β βββββββ€ βββββββ€ β β β Arithmetic Unit β β β
β β β R2 β β R3 β β β β (+, -, *, /) β β β
β β βββββββ€ βββββββ€ β β βββββββββββββββββββββββββββ€ β β
β β β ... β β ... β β β β Logic Unit β β β
β β βββββββ€ βββββββ€ β β β (AND, OR, XOR, NOT) β β β
β β β PC β β IR β β β βββββββββββββββββββββββββββ€ β β
β β βββββββ βββββββ β β β Shift Unit β β β
β β β β β (<<, >>) β β β
β βββββββββββββββββββββββ βββββββββββββββββββββββββββββββββββ β
β β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β Internal Bus β β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β
βββββββββββ΄ββββββββββ
β System Bus β
βββββββββββββββββββββ
1.2 ALU (Arithmetic Logic Unit)¶
The ALU is the core component in the CPU that performs actual computations.
ββββββββββββββββ
A ββββββββββΊβ β
(Operand 1) β β
β ALU ββββββββββΊ Result
B ββββββββββΊβ β
(Operand 2) β ββββββββββΊ Status Flags
β β (Zero, Carry,
Op Code ββββΊβ β Overflow, Sign)
ββββββββββββββββ
Operations Performed by ALU¶
| Operation Type | Operation | Description |
|---|---|---|
| Arithmetic | ADD | Addition |
| SUB | Subtraction | |
| MUL | Multiplication | |
| DIV | Division | |
| INC | Increment by 1 | |
| DEC | Decrement by 1 | |
| Logical | AND | Logical AND |
| OR | Logical OR | |
| XOR | Exclusive OR | |
| NOT | Logical NOT | |
| Shift | SHL | Shift Left |
| SHR | Shift Right (Logical) | |
| SAR | Shift Right (Arithmetic) | |
| Comparison | CMP | Compare (subtract and set flags) |
Status Flags Register¶
βββββ¬ββββ¬ββββ¬ββββ¬ββββ¬ββββ¬ββββ¬ββββ
β S β Z β - β A β - β P β - β C β
βββββ΄ββββ΄ββββ΄ββββ΄ββββ΄ββββ΄ββββ΄ββββ
β β β β β
β β β β ββ Carry (carry/borrow)
β β β ββββββββββ Parity
β β ββββββββββββββββββ Auxiliary Carry
β ββββββββββββββββββββββββββ Zero (result is 0)
ββββββββββββββββββββββββββββββ Sign (negative if 1)
Additional flags:
- Overflow (O): Overflow occurred
- Interrupt (I): Interrupt enable
- Direction (D): String operation direction
1.3 Control Unit¶
The control unit decodes instructions and sends appropriate control signals to each component.
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β Control Unit (CU) β
β β
β βββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β Instruction Register (IR) β β
β β ββββββββββββββ¬βββββββββββββ¬βββββββββββββββββ β β
β β β Opcode β Rs/Rd β Immediate β β β
β β β (Operation)β (Registers)β (Value) β β β
β β ββββββββββββββ΄βββββββββββββ΄βββββββββββββββββ β β
β βββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β β
β βΌ β
β βββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β Instruction Decoder β β
β βββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β β
β βββββββββββββββββΌββββββββββββββββ β
β βΌ βΌ βΌ β
β ββββββββββββ ββββββββββββ ββββββββββββ β
β β ALU β β Register β β Memory β β
β β Control β β Control β β Control β β
β ββββββββββββ ββββββββββββ ββββββββββββ β
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
Control Signal Examples¶
| Control Signal | Function |
|---|---|
| RegWrite | Enable register write |
| ALUSrc | Select ALU input source |
| ALUOp | Specify ALU operation type |
| MemRead | Enable memory read |
| MemWrite | Enable memory write |
| MemtoReg | Select memory-to-register path |
| Branch | Branch decision |
| Jump | Jump decision |
2. Register Types¶
2.1 General Purpose Registers¶
Registers that programmers can use freely.
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β General Purpose Registers (x86-64) β
βββββββββββββββ¬ββββββββββ¬ββββββββββ¬βββββββββββββββββββββββββββββββ€
β 64-bit β 32-bit β 16-bit β Purpose β
βββββββββββββββΌββββββββββΌββββββββββΌβββββββββββββββββββββββββββββββ€
β RAX β EAX β AX β Accumulator (arithmetic) β
β RBX β EBX β BX β Base (memory address base) β
β RCX β ECX β CX β Counter (loop counter) β
β RDX β EDX β DX β Data (I/O operations) β
β RSI β ESI β SI β Source Index β
β RDI β EDI β DI β Destination Index β
β RBP β EBP β BP β Base Pointer (stack frame) β
β RSP β ESP β SP β Stack Pointer β
β R8-R15 β R8D-R15Dβ R8W-R15Wβ Additional GPRs (x64) β
βββββββββββββββ΄ββββββββββ΄ββββββββββ΄βββββββββββββββββββββββββββββββ
Register Size Relationships (x86)¶
64-bit: ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ€ RAX
32-bit: ββββββββββββββββββββββββββββ€ EAX
16-bit: ββββββββββββ€ AX
8-bit: ββββββ¬ββββββ€
AH AL
2.2 Special Purpose Registers¶
Registers essential for processor operation.
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β Special Purpose Registers β
ββββββββββββββββ¬βββββββββββββββββββββββββββββββββββββββββββββββββββ€
β Register β Role β
ββββββββββββββββΌβββββββββββββββββββββββββββββββββββββββββββββββββββ€
β PC (Program β Stores address of next instruction to execute β
β Counter) β Automatically incremented after fetch β
ββββββββββββββββΌβββββββββββββββββββββββββββββββββββββββββββββββββββ€
β IR (Instruc- β Stores the currently executing instruction β
β tion Reg.) β Target for control unit decoding β
ββββββββββββββββΌβββββββββββββββββββββββββββββββββββββββββββββββββββ€
β MAR (Memory β Stores memory address to access β
β Address Reg.)β Connected to address bus β
ββββββββββββββββΌβββββββββββββββββββββββββββββββββββββββββββββββββββ€
β MBR/MDR β Stores data to read or write from memory β
β (Memory Data)β Connected to data bus β
ββββββββββββββββΌβββββββββββββββββββββββββββββββββββββββββββββββββββ€
β SP (Stack β Stores address of top of stack β
β Pointer) β Automatically adjusted during PUSH/POP β
ββββββββββββββββΌβββββββββββββββββββββββββββββββββββββββββββββββββββ€
β PSW/FLAGS β Stores processor status information β
β (Status Reg.)β Flags like Zero, Carry, Overflow β
ββββββββββββββββ΄βββββββββββββββββββββββββββββββββββββββββββββββββββ
PC (Program Counter) Operation¶
Memory: PC Operation:
βββββββββββββββ
β 0x1000: ADD β ββββ PC = 0x1000 (current)
βββββββββββββββ€
β 0x1004: SUB β ββββ PC = 0x1004 (next)
βββββββββββββββ€
β 0x1008: MUL β ββββ PC = 0x1008
βββββββββββββββ€
β 0x100C: JMP β ββββ PC value changes on branch
βββββββββββββββ€
β ... β
βββββββββββββββ
Sequential execution: PC = PC + instruction size
Branch execution: PC = branch target address
2.3 ARM Register Structure¶
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β ARM Registers (AArch64) β
ββββββββββββββββ¬βββββββββββββββββββββββββββββββββββββββββββββββββββ€
β Register β Role β
ββββββββββββββββΌβββββββββββββββββββββββββββββββββββββββββββββββββββ€
β X0 - X7 β Argument passing and return value registers β
β X8 β Indirect result register β
β X9 - X15 β Temporary registers (caller-saved) β
β X16 - X17 β Intra-procedure call registers β
β X18 β Platform register β
β X19 - X28 β Callee-saved registers β
β X29 (FP) β Frame Pointer β
β X30 (LR) β Link Register (return address) β
β SP β Stack Pointer β
β PC β Program Counter β
ββββββββββββββββ΄βββββββββββββββββββββββββββββββββββββββββββββββββββ
3. Datapath¶
3.1 Datapath Concept¶
The datapath is the collection of paths through which data moves within the CPU and the functional units that process data along these paths.
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β Basic Datapath β
β β
β ββββββββ ββββββββββββββββ β
β β PC ββββββββββΊβ Instruction β β
β ββββββββ β Memory β β
β β ββββββββ¬ββββββββ β
β β β β
β βΌ βΌ β
β ββββββββ ββββββββββββββββ ββββββββββββββββ β
β β +4 β β Instruction ββββββββββΊβ Control β β
β ββββββββ β IR β β Unit β β
β ββββββββ¬ββββββββ ββββββββ¬ββββββββ β
β β β β
β βΌ βΌ β
β βββββββββββββββββ Control Signals β
β βββββββββββ€ Register β β
β β β File β β
β β βββββ¬ββββββββ¬ββββ β
β β β β β
β β βΌ βΌ β
β β βββββββββββββββββ β
β β β ALU β β
β β βββββββββ¬ββββββββ β
β β β β
β β βΌ β
β β βββββββββββββββββ β
β ββββββββββΊβ Data β β
β β Memory β β
β βββββββββββββββββ β
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
3.2 MIPS Datapath (Detailed)¶
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β MIPS Datapath β
β β
β β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β Instruction Fetch (IF) β β
β β β β
β β ββββββββ ββββββββ ββββββββββββββββββ β β
β β β PC βββββΊβ +4 β β Instruction β β β
β β ββββββββ βββββ¬βββ β Memory β β β
β β β β ββββββββββ¬ββββββββ β β
β β βββββββββββββ΄βββββββββββββββββ β β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β β
β βΌ [31:0] Instruction β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β Instruction Decode (ID) β β
β β β β
β β [25:21] ββββββββββββββββ β β
β β βββββββββΊβ Read βββββΊ Read Data 1 β β
β β [20:16] β Register β β β
β β βββββββββΊβ File βββββΊ Read Data 2 β β
β β [15:11] β β β β
β β βββββββββΊβ Write Reg ββββ Write Data β β
β β ββββββββββββββββ β β
β β β β
β β [15:0] ββββββββββββββββ β β
β β βββββββββΊβ Sign βββββΊ 32-bit immediate β β
β β β Extend β β β
β β ββββββββββββββββ β β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β β
β βΌ β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β Execute (EX) β β
β β β β
β β Read Data 1 ββββΊββββββββββββββββ β β
β β β β β β
β β MUX Output ββββΊβ ALU βββββΊ ALU Result β β
β β β βββββΊ Zero Flag β β
β β ββββββββββββββββ β β
β β β β
β β Read Data 2 ββββΊββββββββ β β
β β Immediate ββββΊβ MUX βββββΊ ALU Input B β β
β β ββββββββ β β
β β β² ALUSrc β β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β β
β βΌ β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β Memory Access (MEM) β β
β β β β
β β ALU Result ββββββΊββββββββββββββββββ β β
β β (Address) β Data βββββΊ Read Data β β
β β β Memory β β β
β β Write Data ββββββΊβ β β β
β β ββββββββββββββββββ β β
β β β² MemRead/MemWrite β β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β β
β βΌ β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β Write Back (WB) β β
β β β β
β β ALU Result ββββΊββββββββ β β
β β Memory Data ββββΊβ MUX βββββΊ Register File Write Data β β
β β ββββββββ β β
β β β² MemtoReg β β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
3.3 Datapath Components¶
| Component | Function | Control Signal |
|---|---|---|
| PC | Store next instruction address | - |
| Instruction Memory | Store and provide instructions | - |
| Register File | Register read/write | RegWrite |
| ALU | Arithmetic/logical operations | ALUOp |
| Data Memory | Store/load data | MemRead, MemWrite |
| MUX | Select data path | ALUSrc, MemtoReg |
| Sign Extend | 16-bit β 32-bit extension | - |
4. Instruction Execution Cycle Details¶
4.1 Basic Execution Cycle¶
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β Instruction Execution Cycle β
β β
β ββββββββββ ββββββββββ ββββββββββ ββββββββββ ββββββββ β
β β Fetch ββββΊβ Decode ββββΊβExecute ββββΊβ Memory ββββΊβWrite β β
β β β β β β β β Access β βBack β β
β ββββββββββ ββββββββββ ββββββββββ ββββββββββ ββββββββ β
β β β β
β βββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β Repeat β
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
4.2 Each Stage in Detail¶
Stage 1: Instruction Fetch (IF)¶
Operation:
1. Copy PC value to MAR
2. Read Memory[MAR] content to MBR
3. Copy MBR content to IR
4. PC = PC + instruction size
Micro-operations:
MAR β PC
MBR β Memory[MAR]
IR β MBR
PC β PC + 4
Timing Diagram:
ββββββ¬ββββββ¬ββββββ¬ββββββ¬βββββ
T0 β T1 β T2 β T3 β
ββββββ΄ββββββ΄ββββββ΄ββββββ΄βββββ
MARβPC MBRβMem IRβMBR PCβPC+4
Stage 2: Instruction Decode (ID)¶
Operation:
1. Analyze IR opcode field
2. Calculate operand addresses
3. Read required register values
Micro-operations:
A β Regs[IR[25:21]] // Read rs register
B β Regs[IR[20:16]] // Read rt register
ALUOut β PC + (sign-extend(IR[15:0]) << 2) // Calculate branch address
Instruction Format Analysis (MIPS):
ββββββββββ¬ββββββββ¬ββββββββ¬ββββββββ¬ββββββββ¬βββββββββ
β opcode β rs β rt β rd β shamt β funct β R-type
β 6-bit β 5-bit β 5-bit β 5-bit β 5-bit β 6-bit β
ββββββββββ΄ββββββββ΄ββββββββ΄ββββββββ΄ββββββββ΄βββββββββ
ββββββββββ¬ββββββββ¬ββββββββ¬ββββββββββββββββββββββββββ
β opcode β rs β rt β immediate β I-type
β 6-bit β 5-bit β 5-bit β 16-bit β
ββββββββββ΄ββββββββ΄ββββββββ΄ββββββββββββββββββββββββββ
Stage 3: Execute (EX)¶
Execution by instruction type:
1. Arithmetic/Logic Operations (R-type):
ALUOut β A op B
Example: ADD $t0, $t1, $t2
ALUOut β Regs[$t1] + Regs[$t2]
2. Memory Reference:
ALUOut β A + sign-extend(IR[15:0])
Example: LW $t0, 100($t1)
ALUOut β Regs[$t1] + 100
3. Branch:
if (A == B) PC β ALUOut
Example: BEQ $t0, $t1, label
if (Regs[$t0] == Regs[$t1])
PC β PC + offset Γ 4
Stage 4: Memory Access (MEM)¶
Load Instruction:
MDR β Memory[ALUOut]
Example: LW $t0, 100($t1)
MDR β Memory[Regs[$t1] + 100]
Store Instruction:
Memory[ALUOut] β B
Example: SW $t0, 100($t1)
Memory[Regs[$t1] + 100] β Regs[$t0]
Stage 5: Write Back (WB)¶
R-type Instruction:
Regs[IR[15:11]] β ALUOut
Example: ADD $t0, $t1, $t2
Regs[$t0] β ALUOut
Load Instruction:
Regs[IR[20:16]] β MDR
Example: LW $t0, 100($t1)
Regs[$t0] β MDR
4.3 Instruction Execution Examples¶
Example: ADD $t0, $t1, $t2 (R-type)
Stage 1 (IF):
MAR β PC
IR β Memory[MAR]
PC β PC + 4
Stage 2 (ID):
A β Regs[$t1]
B β Regs[$t2]
Stage 3 (EX):
ALUOut β A + B
Stage 4 (MEM):
(None - no memory access needed)
Stage 5 (WB):
Regs[$t0] β ALUOut
Example: LW $t0, 100($t1) (I-type, Load)
Stage 1 (IF):
MAR β PC
IR β Memory[MAR]
PC β PC + 4
Stage 2 (ID):
A β Regs[$t1]
Stage 3 (EX):
ALUOut β A + 100
Stage 4 (MEM):
MDR β Memory[ALUOut]
Stage 5 (WB):
Regs[$t0] β MDR
5. Single-Cycle vs Multi-Cycle¶
5.1 Single-Cycle Implementation¶
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β Single-Cycle β
β β
β Feature: All instructions complete in one clock cycle β
β β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β 1 Clock Cycle β β
β β βββββββ¬ββββββ¬ββββββ¬ββββββ¬ββββββ β β
β β β IF β ID β EX β MEM β WB β β β
β β βββββββ΄ββββββ΄ββββββ΄ββββββ΄ββββββ β β
β ββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ β
β β
β Clock Period = Execution time of longest instruction (Load) β
β β
β Example (time for each stage): β
β - IF: 200ps β
β - ID: 100ps β
β - EX: 200ps β
β - MEM: 200ps β
β - WB: 100ps β
β β
β Clock Period = 200 + 100 + 200 + 200 + 100 = 800ps β
β β
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
Single-Cycle Advantages and Disadvantages¶
| Advantages | Disadvantages |
|---|---|
| Simple implementation | Long clock period (based on slowest instruction) |
| Simple control logic | All instructions take same time |
| CPI = 1 (1 cycle per instruction) | Low hardware resource utilization |
5.2 Multi-Cycle Implementation¶
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β Multi-Cycle β
β β
β Feature: Instructions execute over multiple clock cycles β
β β
β Each stage in a separate cycle: β
β βββββββ βββββββ βββββββ βββββββ βββββββ β
β β IF β β ID β β EX β β MEM β β WB β β
β βββββββ βββββββ βββββββ βββββββ βββββββ β
β Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 β
β β
β Clock Period = Time of longest stage β
β = max(200, 100, 200, 200, 100) = 200ps β
β β
β Cycles per instruction type: β
β - Load: 5 cycles (IF, ID, EX, MEM, WB) β
β - Store: 4 cycles (IF, ID, EX, MEM) β
β - R-type: 4 cycles (IF, ID, EX, WB) β
β - Branch: 3 cycles (IF, ID, EX) β
β β
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
Multi-Cycle State Diagram¶
βββββββββββββββββββββββββββββββββββ
β β
βΌ β
ββββββββββββ β
β IF β β
β (Fetch) β β
ββββββ¬ββββββ β
β β
βΌ β
ββββββββββββ β
β ID β β
β (Decode) β β
ββββββ¬ββββββ β
β β
βββββββββββΌββββββββββ β
β β β β
βΌ βΌ βΌ β
ββββββββββ ββββββββββ ββββββββββ β
β MEM β β R-type β β Branch βββββββββββββββββ
βAddress β β Exec β βCompleteβ
ββββββ¬ββββ ββββββ¬ββββ ββββββββββ
β β
ββββββ΄βββββ β
β β β
βΌ βΌ β
βββββββββ ββββββββββ
β Load β β Store ββ
β MEM β β MEM ββ
βββββ¬ββββ ββββββββββ
β β
βΌ β
βββββββββ βββββββ΄ββββββ
β Load β β R-type β
β WB β β WB β
βββββββββ βββββββββββββ
5.3 Performance Comparison¶
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
β Performance Comparison Example β
β β
β Assumptions: β
β - Instruction mix: Load 25%, Store 10%, R-type 45%, Branch 20%β
β - Single-cycle clock: 800ps β
β - Multi-cycle clock: 200ps β
β β
β Single-Cycle: β
β Average time = 800ps Γ 1 = 800ps/instruction β
β β
β Multi-Cycle: β
β Average CPI = 0.25Γ5 + 0.10Γ4 + 0.45Γ4 + 0.20Γ3 β
β = 1.25 + 0.40 + 1.80 + 0.60 = 4.05 β
β Average time = 200ps Γ 4.05 = 810ps/instruction β
β β
β Conclusion: Similar performance in this example β
β (But multi-cycle uses hardware resources more efficiently) β
β β
βββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββββ
5.4 Comparison Summary¶
| Feature | Single-Cycle | Multi-Cycle |
|---|---|---|
| CPI | 1 | Variable (3~5) |
| Clock Period | Long (longest instruction) | Short (longest stage) |
| Control Logic | Simple | Complex (FSM required) |
| Hardware Usage | Inefficient | Efficient (shared) |
| Memory | Instruction/data separate | Can be unified |
| Implementation Complexity | Low | Medium |
6. Practice Problems¶
Basic Problems¶
-
What are the three main components of a CPU?
-
Explain the role of the following registers:
- (a) PC (Program Counter)
- (b) IR (Instruction Register)
-
(c) MAR (Memory Address Register)
-
List three types of operations performed by the ALU.
Datapath Problems¶
- For the following MIPS instruction, select all control signals that are activated:
ADD $t0, $t1, $t2
- (a) RegWrite
- (b) ALUSrc
- (c) MemRead
- (d) MemWrite
-
(e) MemtoReg
-
Explain the 5-stage execution process for the instruction
LW $t0, 100($t1)in order.
Performance Analysis Problems¶
- In a single-cycle CPU where each stage takes the following time:
- IF: 250ps
- ID: 150ps
- EX: 200ps
- MEM: 300ps
- WB: 100ps
(a) What is the clock period? (b) How many instructions can be executed in 1 second?
- In a multi-cycle CPU with the following instruction distribution, calculate the average CPI:
- Load: 30% (5 cycles)
- Store: 15% (4 cycles)
- R-type: 40% (4 cycles)
- Branch: 15% (3 cycles)
Advanced Problems¶
-
Explain three CPU design techniques to solve the Von Neumann bottleneck.
-
Calculate the total execution time for the following code sequence in both single-cycle and multi-cycle CPUs (using time assumptions from problem 6):
LW $t0, 0($s0)
ADD $t1, $t0, $t2
SW $t1, 4($s0)
Answers
1. ALU (Arithmetic Logic Unit), Control Unit, Registers 2. - (a) PC: Stores the address of the next instruction to execute - (b) IR: Stores the currently executing instruction - (c) MAR: Stores the memory address to access 3. Arithmetic operations (addition, subtraction, etc.), Logical operations (AND, OR, etc.), Shift operations (or Comparison operations) 4. (a) RegWrite - Activated because result is written to register - ALUSrc = 0 (use register value) - MemtoReg = 0 (select ALU result) 5. - IF: Fetch instruction from PC, PC+4 - ID: Read $t1 register value, sign-extend offset(100) - EX: Calculate address $t1 + 100 - MEM: Read data from calculated address - WB: Store read data to $t0 6. - (a) Clock period = 250 + 150 + 200 + 300 + 100 = 1000ps = 1ns - (b) 1 second / 1ns = 10^9 = 1 GIPS (Giga Instructions Per Second) 7. Average CPI = 0.30Γ5 + 0.15Γ4 + 0.40Γ4 + 0.15Γ3 = 1.50 + 0.60 + 1.60 + 0.45 = 4.15 8. - Cache memory: Place high-speed memory between CPU and memory - Pipelining: Process multiple instructions simultaneously - Prefetching: Fetch required data in advance 9. - Single-cycle: 3 Γ 1000ps = 3000ps = 3ns - Multi-cycle: (5 + 4 + 4) Γ 300ps = 13 Γ 300ps = 3900ps = 3.9ns (Clock period = max(250, 150, 200, 300, 100) = 300ps)Next Steps¶
- 08_Control_Unit.md - Hardwired/Microprogrammed Control
References¶
- Computer Organization and Design (Patterson & Hennessy)
- Computer Architecture: A Quantitative Approach (Hennessy & Patterson)
- CPU Visual Simulator
- MIPS Datapath Simulator