Computer System Overview¶

Overview¶

A computer is an electronic device that receives input data, processes it, and outputs results. In this lesson, we'll learn about the history of computers, their basic structure, and the relationship between hardware and software.

Table of Contents¶

History of Computers
Von Neumann Architecture
Hardware Components
Software Layers
Performance Measurement
Practice Problems

1. History of Computers¶

Evolution by Generation¶

Generation	Period	Core Technology	Characteristics
1st Gen	1940s-1950s	Vacuum tubes	ENIAC, large size, high heat, low reliability
2nd Gen	1950s-1960s	Transistors	Miniaturization, low power, COBOL/FORTRAN
3rd Gen	1960s-1970s	Integrated Circuits (IC)	Operating systems, multiprogramming
4th Gen	1970s-Present	VLSI/ULSI	Microprocessors, personal computers
5th Gen	Present-Future	AI/Quantum computers	Parallel processing, artificial intelligence

Major Milestones¶

1946: ENIAC (first general-purpose electronic computer)
1947: Transistor invented (Bell Labs)
1958: Integrated circuit invented (Jack Kilby)
1971: Intel 4004 (first commercial microprocessor)
1981: IBM PC
2007: iPhone (mobile computing era)

2. Von Neumann Architecture¶

Core Concept¶

The computer architecture proposed by John von Neumann in 1945, which most modern computers follow.

┌─────────────────────────────────────────┐
│              CPU (Central Processing Unit) │
│  ┌─────────┐  ┌─────────┐  ┌─────────┐  │
│  │ Control │  │   ALU   │  │Registers│  │
│  │  Unit   │  │(Arithmetic│  │         │  │
│  │         │  │  Logic  │  │         │  │
│  │         │  │  Unit)  │  │         │  │
│  └─────────┘  └─────────┘  └─────────┘  │
└──────────────────┬──────────────────────┘
                   │ System Bus
     ┌─────────────┼─────────────┐
     │             │             │
┌────┴────┐  ┌─────┴─────┐  ┌────┴────┐
│ Memory  │  │   Input   │  │  Output │
│  (RAM)  │  │ Devices   │  │ Devices │
│         │  │(Keyboard, │  │(Monitor,│
│         │  │   etc.)   │  │  etc.)  │
└─────────┘  └───────────┘  └─────────┘

Core Principles¶

Stored Program Concept: Programs and data stored in the same memory
Sequential Execution: Instructions executed sequentially, one at a time
Binary Representation: All data represented in binary

Von Neumann Bottleneck¶

Data transfer speed between CPU and memory is a performance bottleneck

CPU Speed >> Memory Speed

Solutions:
- Cache memory
- Pipelining
- Multiple buses

3. Hardware Components¶

3.1 Central Processing Unit (CPU)¶

┌────────────────────────────────────────┐
│                  CPU                    │
│  ┌──────────────────────────────────┐  │
│  │      Control Unit (CU)            │  │
│  │  - Instruction decoding           │  │
│  │  - Execution sequence control     │  │
│  │  - Control signal generation      │  │
│  └──────────────────────────────────┘  │
│  ┌──────────────────────────────────┐  │
│  │  Arithmetic Logic Unit (ALU)      │  │
│  │  - Arithmetic operations (+,-,*,/)│  │
│  │  - Logic operations (AND,OR,NOT)  │  │
│  │  - Comparison operations          │  │
│  └──────────────────────────────────┘  │
│  ┌──────────────────────────────────┐  │
│  │         Registers                 │  │
│  │  - PC (Program Counter)           │  │
│  │  - IR (Instruction Register)      │  │
│  │  - AC (Accumulator)               │  │
│  │  - MAR, MBR (Memory access)       │  │
│  └──────────────────────────────────┘  │
└────────────────────────────────────────┘

3.2 Main Memory¶

Type	Characteristics	Usage
RAM	Volatile, read/write	Running programs/data
ROM	Non-volatile, read-only	BIOS, firmware
Cache	High-speed, small capacity	Bridge CPU-memory speed gap

3.3 Secondary Storage¶

Type	Speed	Capacity	Characteristics
SSD	Fast	Medium	Flash memory, silent
HDD	Slow	Large	Magnetic disk, inexpensive
USB	Medium	Small	Portable

3.4 Bus System¶

┌───────────────────────────────────────────┐
│              Data Bus                      │
│    (Data transfer between CPU ↔ Memory)   │
├───────────────────────────────────────────┤
│              Address Bus                   │
│    (Memory address specification, unidirectional) │
├───────────────────────────────────────────┤
│              Control Bus                   │
│    (Read/write control signals)           │
└───────────────────────────────────────────┘

4. Software Layers¶

Layer Structure¶

┌─────────────────────────────────┐
│    Application Programs          │  Web browsers, games, word processors
├─────────────────────────────────┤
│    System Software               │  Compilers, libraries
├─────────────────────────────────┤
│    Operating System (OS)         │  Windows, Linux, macOS
├─────────────────────────────────┤
│    Firmware / BIOS               │  Hardware initialization
├─────────────────────────────────┤
│    Hardware                      │  CPU, memory, disk
└─────────────────────────────────┘

Instruction Execution Cycle¶

┌───────────────────────────────────────────────┐
│                                               │
│  ┌─────────┐   ┌─────────┐   ┌─────────┐     │
│  │  Fetch  │ → │ Decode  │ → │ Execute │     │
│  │         │   │         │   │         │     │
│  └─────────┘   └─────────┘   └─────────┘     │
│       ↑                            │          │
│       └────────────────────────────┘          │
│                  Repeat                        │
└───────────────────────────────────────────────┘

1. Fetch:   Retrieve instruction from address pointed to by PC
2. Decode:  Decode instruction, determine required operation
3. Execute: Perform operation in ALU, store result

5. Performance Measurement¶

Key Metrics¶

Metric	Description	Unit
Clock Speed	Clock cycles per second	Hz (GHz)
CPI	Cycles per instruction	cycles/instruction
MIPS	Million instructions per second	million instructions/sec
FLOPS	Floating-point operations per second	floating point ops/sec

Performance Calculation Formulas¶

CPU Time = Instruction Count × CPI × Clock Period

         Instruction Count × CPI
CPU Time = ───────────────────────
            Clock Speed

Example:
- Instruction count: 1 billion
- CPI: 2
- Clock speed: 4GHz

CPU Time = (10^9 × 2) / (4 × 10^9) = 0.5 seconds

Amdahl's Law¶

Overall Speedup = 1 / ((1 - P) + P/S)

P: Fraction of program that can be improved
S: Speedup factor for that fraction

Example: Improve 80% of program to run 2× faster
= 1 / ((1 - 0.8) + 0.8/2)
= 1 / (0.2 + 0.4)
= 1.67× speedup

6. Practice Problems¶

Basic Problems¶

What are the five components of Von Neumann architecture?
Which of the following is volatile memory?
(a) ROM
(b) RAM
(c) SSD
(d) HDD
Which part of the CPU decodes instructions?

Calculation Problems¶

If a CPU has a clock speed of 3GHz and CPI of 1.5, how long does it take to execute 900 million instructions?
If 70% of a program can be parallelized and runs on 4 cores, what is the maximum speedup according to Amdahl's Law?

Advanced Problems¶

Describe three methods to solve the Von Neumann bottleneck.
Explain the differences between Harvard architecture and Von Neumann architecture.

Answers

1. Input devices, output devices, memory, arithmetic logic unit (ALU), control unit 2. (b) RAM 3. Control Unit 4. (9×10^8 × 1.5) / (3×10^9) = 0.45 seconds 5. 1 / ((1-0.7) + 0.7/4) = 1 / (0.3 + 0.175) = 2.1× 6. Cache memory, pipelining, multiple buses, Harvard architecture 7. Harvard architecture stores instructions and data in separate memories and accesses them via separate buses

Next Steps¶

02_Data_Representation_Basics.md - Binary numbers and base conversion

References¶

Computer Organization and Design (Patterson & Hennessy)
Crash Course: Computer Science
Nand2Tetris